A reverse blocking IGBT (RB-IGBT: Reverse Blocking Insulated Gate Bipolar Transistor) needs to ensure a reverse blocking performance equal to a forward blocking performance in order to guarantee a breakdown voltage even when a reverse voltage is applied. In order to ensure the reverse blocking performance, a pn junction is formed in the reverse blocking IGBT by a diffusion layer (hereinafter, referred to as a separation layer) which passes through a semiconductor chip in a direction vertical to the main surface and separates the side surface of the semiconductor chip from a drift layer. The reverse breakdown voltage of the reverse blocking semiconductor device is maintained by the pn junction.
Next, a method of manufacturing (fabricating) the reverse blocking IGBT will be described (hereinafter, referred to as a first manufacturing method). FIGS. 8 to 12 are cross-sectional views illustrating the reverse blocking IGBT according to the related art which is being manufactured and illustrate a method of diffusing a dopant from an impurity source (liquid diffusion source) which is applied onto a semiconductor wafer (application and diffusion method) to form a separation layer. First, as illustrated in FIG. 8, an oxide film 2 with a thickness of, for example, about 2.5 μm is formed on the front surface of an n-type semiconductor wafer 1 by a thermal oxidation method using a dopant mask.
Then, as illustrated in FIG. 9, the oxide film 2 is selectively removed by photolithography to form an opening 3 for forming a separation layer. Then, as illustrated in FIG. 10, a boron (B) source 4 is applied onto the oxide film 2 such that the boron source 4 is provided in the opening 3. Then, the semiconductor wafer 1 is inserted into a diffusion furnace and a thermal diffusion process is performed at a high temperature (for example, 1300° C.) for a long time (for example, 100 hours). Boron of the boron source 4 is diffused from the opening 3 of the oxide film 2 into the semiconductor wafer 1 by the thermal diffusion process to form a p-type diffusion layer, which is a separation layer 5 with a thickness of, for example, about several hundreds of micrometers, in a surface layer of the front surface of the semiconductor wafer 1.
Then, as illustrated in FIG. 11, the boron source 4 and the oxide film 2 are removed and a front surface element structure (not illustrated) of the reverse blocking IGBT is formed on the front surface of the semiconductor wafer 1. Then, the rear surface of the semiconductor wafer 1 is ground until the separation layer 5 is exposed to thin the semiconductor wafer 1. Then, as illustrated in FIG. 12, a rear surface element structure including a p+ collector region 6 and a collector electrode is formed on the ground rear surface of the semiconductor wafer 1. Then, the semiconductor wafer 1 is diced into dicing chips along a dicing line (not illustrated) formed at the center of the separation layer 5. In this way, the reverse blocking IGBT having the separation layer 5 on the side surface of the chip is completed.
Next, another method of manufacturing the reverse blocking IGBT will be described (hereinafter, referred to as a second manufacturing method). FIGS. 13 to 16 are cross-sectional views illustrating another example of the reverse blocking IGBT according to the related art which is being manufactured and illustrate a method of implanting impurity ions into a semiconductor wafer and diffusing them to form a separation layer. First, as illustrated in FIG. 13, an oxide film 12 with a thickness of, for example, about 1 μm is formed on the front surface of an n-type semiconductor wafer 11 by a thermal oxidation method using a dopant mask.
Then, as illustrated in FIG. 14, the oxide film 12 is selectively removed by photolithography to form an opening 13 for forming a separation layer. Then, as illustrated in FIG. 15, boron ions 14 are implanted into the semiconductor wafer 11 using the oxide film 12 as a mask. The dose of ions 14 implanted may be, for example, about 1×105 cm−2. Then, as illustrated in FIG. 16, the semiconductor wafer 11 is inserted into a diffusion furnace and a thermal diffusion process is performed at a high temperature (for example, 1300° C.) for a long time (for example, 100 hours). Boron implanted into the semiconductor wafer 11 is diffused by the thermal diffusion process to form a p-type diffusion layer, which is a separation layer 15 with a thickness of, for example, about several hundreds of micrometers, in a surface layer of the front surface of the semiconductor wafer 11.
Then, the oxide film 12 used for ion implantation is removed and a front surface element structure (not illustrated) of the reverse blocking IGBT is formed on the front surface of the semiconductor wafer 11. Then, similarly to the first manufacturing method described above, the rear surface of the semiconductor wafer 11 is ground until the separation layer 15 is exposed (see FIG. 11). Then, as illustrated in FIG. 12, similarly to the first manufacturing method, a p+ collector region 6 and a collector electrode are formed on the ground rear surface of the semiconductor wafer 11 (represented by reference numeral 1 in FIG. 12) and the semiconductor wafer 11 is diced along a dicing line (not illustrated). In this way, the reverse blocking IGBT having the separation layer 15 (represented by reference numeral 5 in FIG. 12) on the side surface of the chip is completed.
In recent years, a method has been proposed which forms a groove in a semiconductor wafer using etching and forms a separation layer on the side wall of the groove, thereby manufacturing a reverse blocking IGBT. In addition, the following method has been proposed. A thin semiconductor wafer in which a front surface structure and a rear surface structure forming a semiconductor chip are formed is attached to a supporting substrate by a double-sided adhesive tape. A trench serving as a scribe line is formed in the thin semiconductor wafer by anisotropic wet etching such that a crystal plane is exposed. A separation layer for maintaining a reverse breakdown voltage is formed on the side surface of the trench from which the crystal plane is exposed by ion implantation and low-temperature annealing or laser annealing such that is comes into contact with a p collector region, which is a rear diffusion layer, and extends to the front surface side. Then, laser dicing is performed to clearly cut the collector electrode below the separation layer without excess or deficiency. Then, the double-sided adhesive tape peels off from the collector electrode to obtain the semiconductor chip. In this way, a reverse blocking semiconductor device is formed (for example, see U.S. Pat. No. 7,741,192).
Furthermore, as another method of manufacturing the reverse blocking IGBT, the following method has been proposed. The front surface of a thin semiconductor wafer in which a front surface structure forming a semiconductor chip is formed is attached to a supporting substrate by a double-sided adhesive tape. A trench serving as a scribe line is formed in the rear surface of the thin semiconductor wafer by anisotropic wet etching such that a crystal plane is exposed. A separation layer for maintaining a reverse breakdown voltage is formed on the side surface of the trench from which the crystal plane is exposed by ion implantation and low-temperature annealing or laser annealing at the same time as a p collector region, which is a rear diffusion layer, is formed. Then, the double-sided adhesive tape peels off from the collector electrode to obtain the semiconductor chip. In this way, a reverse blocking semiconductor device is formed (for example, see JP 2006-303410 A).
As another method of manufacturing the reverse blocking IGBT, a method has been proposed which includes: a first semiconductor region forming step of forming a second-conductivity-type first semiconductor region in a first main surface of a first-conductivity-type wafer; a front surface element structure forming step of forming a front surface element structure on the first main surface of the wafer; a concave portion forming step of forming a concave portion which extends from the second main surface of the wafer to the first semiconductor region; a second semiconductor region forming step of forming a second-conductivity-type second semiconductor region in the second main surface of the wafer so as to be electrically connected to the first semiconductor region; and a cutting step of removing a portion of the first semiconductor region and cutting the wafer into chips. In the cutting step, the first semiconductor region is removed such that the cutting plane of the first semiconductor region is inclined with reference to the first main surface of the wafer (for example, see JP 2011-181770 A).
The reverse blocking IGBT illustrated in FIG. 17 is manufactured by the techniques disclosed in U.S. Pat. No. 7,741,192; JP 2006-303410 A and JP 2011-181770 A. FIG. 17 is a cross-sectional view illustrating the structure of the reverse blocking IGBT according to the related art. As illustrated in FIG. 17, a region of a semiconductor wafer including a dicing line is removed in a groove shape by etching, thereby forming a side surface 22 of a semiconductor chip 21 forming the reverse blocking IGBT. A p+ region 23 forming, for example, a breakdown voltage structure is provided in a front-side surface layer of the side surface 22 of the semiconductor chip 21.
A p+ collector region 24 is formed on the rear surface of the semiconductor chip 21. A p+ separation layer 25 is provided on the side surface 22 of the semiconductor chip 21 and connects the p+ region 23 provided in the front surface of the semiconductor chip 21 and the p+ collector region 24 provided on the rear surface of the semiconductor chip 21. When the p+ separation layer 25 is formed by the techniques disclosed in U.S. Pat. No. 7,741,192; JP 2006-303410 A and JP 2011-181770 A, in many cases, a thermal diffusion process is performed at a high temperature for a long time to form the p+ separation layer 25, similarly to when the separation layer is formed by the above-mentioned first and second manufacturing methods.
Furthermore, as a method of forming the separation layer, a method has been proposed which includes: a first diffusion step of performing deposition on a wafer surface with a wafer plane orientation (111) or (100) in an impurity atmosphere, for a wafer which is sliced with a predetermined thickness from a silicon single crystal ingot having a crystal axis <111> or <100> and whose both surfaces are simultaneously lapped with an abrasive so as to have a uniform processing strain; and a second diffusion step of processing the wafer subjected to the first diffusion step at a temperature of 1250° C. to 1310° C. for 20 hours to 450 hours in a mixed gas atmosphere including 0.5 to 10 (vol) % of O2 gas and Ar or He such that a layer in which no impurity diffused is formed at the center of the wafer and layers in which impurities are diffused are formed on both surfaces of the wafer (for example, see JP 2607853 B1).
As another method of forming the separation layer, a semiconductor silicon wafer manufacturing method has been proposed which includes a first diffusion step of shallowly depositing N impurities on both surfaces of a lapped silicon semiconductor wafer; and a second diffusion step of performing a heat treatment on the wafer at a high temperature for a long time to obtain a necessary diffusion depth and concentration in the surface of the wafer. In the first diffusion step, a diffusion source of N impurities in the wafer is phosphorous in phosphorous oxychloride, phosphorous oxychloride vapor is continuously supplied together with Ar gas including 0.5% or more of O2 gas, the temperature is maintained in the range of 1100° C. to 1300° C., and diffusion is performed for a predetermined time such that a target diffusion depth and a target wafer surface concentration are obtained after the second diffusion step (for example, see JP 2975912 B1).
As a method of forming the separation layer without performing a thermal diffusion process at a high temperature for a long time, a method has been proposed which forms a trench in the front surface of a semiconductor wafer using etching, forms a diffusion layer serving as a separation layer on the bottom and side wall of the trench, and leaves the diffusion layer on the side wall of the trench as the separation layer (hereinafter, referred to as a third manufacturing method).